-- 8-bit up-down counter for 2-phase rotary encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter8b is
    Port ( A : in std_logic;
           B : in std_logic;
		 CLK: in std_logic;
           OUTPUT : out std_logic_vector(0 to 7));
end counter8b;

architecture RTL of counter8b is

signal COUNT: std_logic_vector(7 downto 0);
signal State: std_logic_vector(1 downto 0);
signal DATA: std_logic_vector(3 downto 0);
signal last_direction: bit;

begin
	DATA <= A & B & State;
	OUTPUT <= COUNT;
	process(CLK, A, B) begin
		if(CLK'event and CLK='1') then
			case DATA is
				when "0001"
					| "0111"
					| "1110"
					| "1000" =>
						COUNT <= COUNT + 1;
						last_direction <= '1';
				when "0100"
					| "1101"
					| "1011"
					| "0010" => COUNT <= COUNT - 1;
						last_direction <= '0';
				when "0110"
					| "1001"
					| "1100"
					| "0011" =>
					if(last_direction = '1') then
						COUNT <= COUNT + 2;
					else
						COUNT <= COUNT - 2;
					end if;
				when others=> COUNT <= COUNT;
			end case;
			State <= A & B;
		end if;
	end process;
end RTL;